GPU Cache Hierarchy Design Verification Engineer
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![]() United States, Texas, Austin | |
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Summary
Posted: Aug 29, 2024 Role Number: 200449014 Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Engineering group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you will be responsible for crafting and building the technology that fuels Apple's devices. Together, we will enable our customers to do all the things they love with their devices. The GPU Cache Design Verification Engineer is responsible for the pre-silicon RTL verification of cache hierarchy and related units in a low power GPU design. This includes deep understanding of the micro-architectural details of these units, interactions between the units, and the connection of the uarch to the larger architectural intent of the GPU. A strong computer architecture background, experience in cache and memory subsystem verification, software engineering skills, and a proven foundation in verification methodology will be used to close testing coverage with high confidence. Description As a GPU Cache Hierarchy Design Verification Engineer, you will be responsible for: - Owning testing of major features and collaborating with other block and core level engineers to ensure flawless verification flow - Developing verification plans in coordination with design leads and architects - Architecting, building and maintaining verification test bench components and environments to validate architectural correctness of the design - Generating directed and constrained random tests - Running simulations and debugging design and environment issues - Crafting functional coverage points, analyze coverage, and improve test environment to target coverage holes - Crafting automated verification flows for block verification - Applying knowledge of hardware description languages (VHDL/Verilog), hardware verification languages/frameworks (SystemVerilog/UVM/OVM), and logic simulators to verify sophisticated designs - Mentoring junior engineers to grow their skillsets Key Qualifications
Education & Experience BS + minimum of 3 years of experience Additional Requirements More
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