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Analog Layout Design Engineer

Synopsys
United States, Massachusetts, Boxborough
January 20, 2023

Analog Layout Design Engineer

40051BR

USA - Massachusetts - Boxborough

Job Description and Requirements

We are looking for a staff analog & mixed signal layout mask designer to work within a small well-rounded team on advanced technology nodes for the DDR PHY team.

Responsibilities:

Candidate would oversee the complete design of large full custom analog mixed signal layout blocks. Working collaboratively with circuit design engineers to meet product schedules. Driving the creation from the beginning floor planning stage to routing, physical verification (LVS/DRC/ERC), running in-house quality checks and final checklist. Will need to direct and review work from other team members locally and across sites giving daily guidance and feedback. Will also need to pass on weekly status to the program managers. The candidate would also contribute to the overall development of layout flows, automation and methodology within the layout organization.

Requirements:
  • Typically requires a minimum of 5+ years of related experience.
  • Has a solid desire to learn and explore advanced deep submicron technology nodes.
  • Demonstrates good investigation and problem-solving skills.
  • Has good communication and documentation skills.
  • Builds productive internal/external working relationships. Contacts are primarily within business unit and occasional organizational and external customer contacts on routine matters.
  • Would need to work semi-autonomous and be able to direct and collaborate with remote layout resources.
  • Must have a solid working knowledge of DRC, LVS and be able to debug results.
  • Prior knowledge and proficiency of schematic driven layout editor tools such as Virtuoso XL or Custom Compiler SDL is required.
  • Must be familiar with creating quality layout with consideration for device matching, DFM and current requirements (EMIR).
  • Should be familiar with using foundry design rule manuals to debug DRC errors. Working knowledge of PERC, latch-up risks and related ESD components for I/O pads is highly desired.
  • Other pluses are:
    • TCL, SKILL, Python or other language scripting.
    • Experience with MS Office tools like PowerPoint, SharePoint, Visio, Word, etc.
The base salary range across the U.S. for this role is between $117,000 to $204,000. In addition, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

Job Category

Engineering

Country

United States

Job Subcategory

Layout Design

Hire Type

Employee

Base Salary Range

$117,000 - $204,000

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