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Embedded Memory Architect
USA - California - Mountain View/Sunnyvale Job Description and Requirements At Synopsys, we're at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we're powering it all with the world's most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
Our Embedded memory business is all about building high-performance low power / ultra high density designs to meet the demanding SOC requirement, We're the world's leading provider of solutions for designing and verifying embedded memories to support the need of today's SOC need and we design the next-generation memory architecture to meet the customer requirements. We enable our customers to optimize chips for power, cost, and performance.
A successful candidate will join Embedded memory team and be responsible for architecting the next generation memories and will also work with the team to verify the designs for robustness .The candidate should have extensive experience in overall memory designs and methodologies covering both front-end and back-end implementation We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why EM team is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.
Key qualifications and responsibility:
Key Qualification
- BS / MS in Electrical or Computer Engineering or equivalent experience
- 15+ Year of relevant experience
- Solid understanding of industry-standard design tools.
- Good understanding of Digital Circuit design techniques in FinFet technologies.
- Proven experience on transistor-level circuit design and circuit behavior analysis
- Knowledge of high-performance and low power circuit designs
- Experience developing caches/SRAM design for low voltage and low power operating conditions.
- Exposure to complete design cycle of SRAM memory and compiler development
- Deep understanding of nanometer device physics, leakage mechanisms, technology interactions with device behavior.
- Hands-on experience running SPICE simulation, and capability to adapt to new simulation tools
- Strong proficiency in scripting language, such as, Perl, Tcl, Make, and automation methods/algorithms a certain plus
- Familiar with EMIR/Aging/Self heating and their impacts to circuit/layout implementations and signoff flows
- Great team-work, communication and analytical skills
- Willingness to collaborate closely with cross functional teams across the globe
Responsibility
- Define various architecture/topologies optimizing for power, timing, area, yield and deep dive with the team in optimizing for various memory architecture
- Work with the flow and methodology team to streamline design automation, data collection and analysis, and ensure high yielding silicon
- Supervise layout engineers and review layout for optimality.
- Support post-silicon effort to enable productization.
The base salary range across the U.S. for this role is between $133,000 to $232,000. In addition, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request.
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability. Job Subcategory R&D Engineering Base Salary Range $133,000 - $232,000 |
Synopsys
April 07, 2023